Webinar: Theme 2 - Heterogeneous 3D Integration
Speakers: Lynford Goddard and Paul Braun
Next generation mobile devices and computing architectures would benefit from ultra-high bandwidth technologies that efficiently transport and process optical signals. Subsurface fabrication can address this challenge by forming volumetric photonic integrated circuits (VPICs) with a more compact aerial footprint than planar on-chip circuits. These 3D optical systems may utilize densely packed low-loss, freeform optical interconnects for high volume data transfer. Our VPIC solution has the added benefit of dense non-intersecting 3D interconnect routing. It offers a generalized I/O interface that can connect disparate electronic and photonic designs while simultaneously enabling future scaling.
In this talk, we will present our ongoing research aimed at reducing the total link loss to < 1 dB, expanding the diversity of available devices, and plans to integrate photonic and electronic devices in collaboration with ASAP PIs. Ultimately, our target is to realize optical packaging with hundreds to thousands of low-loss broadband (1280-1650 nm) polarization-insensitive input/output (I/O) fiber optic ports.
Topic 2: Integrated Photonics on Silicon
Speakers: John Dallesasse and Can Bayram
The heterogeneous integration of III-V materials on to silicon is critical for the electronic-photonic integration and the next-generation optical I/O compute packages. This talk will focus on two technologies for III-V on silicon integration.
In the first part of the talk, we will present our success in carrier wafer bonding wherein III-V epitaxial layers are transferred from a silicon carrier wafer to a silicon host wafer and processed into laser and photodetectors on the host wafer after the transfer process. This process can incorporate the functionality of any III-V device directly on chip, while distinct epitaxial structures could also be incorporated on the same die.
In the second part of the talk, we will showcase our research in bufferless heterogeneous integration (as opposed to conventional thick buffer epitaxy or pick-and-place assembly) of electrically driven photonic devices onto compute packages. Our technology will be the key to overcoming the existing I/O power-performance scaling as it enables high design flexibility, capability, low power consumption, small size, and less weight. We will discuss research targeting electrically driven µLEDs and LDs integrated on CMOS-compatible Si (100) and silicon-on-insulator (SOI) substrate platforms for ultra-low-power photonics, capable of operating temperatures ranging from 0-100°C.
Topic 3: Vertical Cavity Surface Emitting Lasers (VCSELs) on Silicon and Photonic Crystal VCSEL Arrays
Speakers: Kent Choquette and Minjoo Lawrence Lee
Si-photonics and vertical cavity surface emitting lasers (VCSELs) are the two largest rapidly growing high volume optoelectronic manufacturing markets and yet to-date they remain disconnected. Long wavelength (1-2 μm) VCSELs have long been pursued for communication and sensing applications but have challenges of p-type free carrier absorption and the lack of monolithic semiconductor materials to construct a viable distributed Bragg reflector mirror (DBR).
This talk will focus on our research to demonstrate 1.5 μm VCSELs epitaxially grown on silicon using manufacturable processing steps. We will develop porous InP-based DBRs with high index contrast combined with high efficiency InGaAs tunnel junctions, all grown monolithically on silicon substrates. Porous InP-based DBRs represent a unique opportunity to solve a long-standing VCSEL challenge that is clearly differentiated from previous approaches while circumventing the limitations of the present state-of-the-art.
We will also discuss our latest research findings in two-dimensional VCSEL arrays with ultra-narrow divergence of single supermode emission. Our future research will target extending these designs to increase output power and scale up the emission spatial brightness. In addition, we will explore beam steering effects that are enabled in these arrays.